The invention relates generally to a method of forming a gate of a semiconductor device and, more particularly, to a method of forming a gate of a semiconductor device, which can prevent an active region from being damaged during an etch process for gate patterning.
Active research has been conducted on NAND flash memory devices, not only because of non-volatile memory characteristics, enabling the program and erase operations, but also an advantageous structure in terms of high integration.
The NAND flash memory device has a structure in which a floating gate and a control gate are formed over a semiconductor substrate with a dielectric layer being formed therebetween and with a tunnel insulating layer formed under the floating gate.
In this NAND flash memory device, a gate corresponding to a word line or a select line is formed by stacking a gate insulating layer, a floating gate, a dielectric layer, a control gate, etc. over a semiconductor substrate and patterning the stacked layer using a gate etch process. This gate etch process is performed in-situ by changing the gate etch process according to an etch condition suitable for materials for forming each etch target layer.